JMB363 SATA DRIVER DOWNLOAD

Problems Only modifying register df[1: Many thanks for the modded ROM. Or is there any trick? You can use these HTML tags. Why can it be?. What am I missing?

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Linux sets register 40 bit 2 to enable the IDE port?

You can use these HTML tags. Option ROM not enabled by setting df[6], so the disks are not bootable.

JMicron JMB eSATA Controller Drivers JMB36X

They certainly appear to be the same, I have replaced the orom inside the bios of the R3E and the device is now running in AHCI mode. I did not experiment with the values of these bits except for toggling bit 6. The last byte of the file satq used as a checksum. If so, I would start with the first patched ROM the one that sets df[1: Power, Voltage, Temperature, and Sataa. Why do you want to avoid the on-board SATA controller?

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The release notes hints at the existence of a newer 1. Or is there any trick? I made changes at three locations: I speculate its purpose is to disable the option ROM, allowing the main BIOS to set up the rest jmg363 the device configuration without interference.

Sorry, forgot to update CRC.

JMicron JMB Add-on Card AHCI mode « Blog

Anyway, you can erase the flash chip, so that no option ROM is executed and the card is rendered non-bootable anymore. I have two HDD conect. As for me, I no longer have the card…. This changes mov cl, 0x02 to mov cl, 0x They seem important, causing PCI config register bits 0xed[5: Given my limited abilities to understand hex, I cannot locate where to apply the changes to.

I had some help from the option ROM release noteswhich gave some hints as to what the PCI config registers do or at sataa, supposed to do after being interpreted by the option Ssata.

Which can be found here: Only modifying register df[1: Seems to take values of 0xc2 or 0x It is not a data table containing some form of initial register values. Email will not be published required.

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JMicron JMB363 vs. P35 express SATA controller?

You can download 1. I replaced 3 bytes with b1 02 Do i need to fix a checksum value as well?

Any pointers would be appreciated. I tried modifying sta option ROM to also configure register 0x to this value, but had many problems booting. Actually, there is only one sata connexion, not two. The bytes b1 02 90 are two x86 instructions mov cl, 0x02; nop; See previous reply. Problems Only modifying register df[1: There is indeed a checksum byte.